P850 Instruction set -------------------- Bit 0 is the MSB, Bit 15 is the LSB Machine is byte addressed - All words must lie on at even addresses. PC is always even. Branch displacements must be even. Registers : 16 internal CPU registers. Registers 0-7 also called A0-A7, Registers 8-15 called B0-B7 Format 0 instructions can only use Registers 0-7 (R3 is a 3-bit field) Register 0 is the Program counter, Register 15 is the hardware stack pointer used for interrupts, etc. Instruction Formats ------------------- 2 formats, specified by bit 0 of the instruction word Format 0: Short Constant, Shift, I/O and Misc instructions 0 Opcode R3 Data 1 4 3 8 Bits R3 Specifies either the register (0-7) or the condition (for branches, etc) Data is instruction-specific - constants, branch displacements, shift type, I/O address or a fixed parameter Format 1 : Register-Register, Long Constanst, Memory Reference 1 Opcode R1 Mode R2 L/S 1 4 4 2 4 1 Bits R1 Specifies Destination register. Note addresses are scrambled - low 3 bits of register number in bits 5-7, high bit in 8 For conditional branches, Bits 5-7 specify the condition, bit 8 is not used Mode is the Addressing mode R2 specifies the source register, as above L/S is the destination load/store bit - either destination = R1 (L/S=0) or destination = memory word referenced by this instruction (L/S=1) If L/S = 0, instruction is of the form R1 := (R1) Op (M), L/S = 1, .......................... (M) = (R1) Op (M). Mode <> RR Addressing modes: 2nd operand {Called (M) in opcode list) is given as follows Assembler Mode R2 Effective mode code Value Address RR 00 0-15 R2 Register contains value RA 01 0 (P) Long constant (PC (R0) points to operand) RA 01 1-15 (R2) Register contains address of operand DA 10 0 ((P)) Direct address in next word DA 10 1-15 ((P))+(R2) Indexed Address IA 11 0 [((P))] Indirect Address : next word contains address of address of memory word to be used IA 11 1-15 [((P))+(R2)] Indirect Indexed Address P = PC = Register A0 R2 = Register specified by bits 11-14 of instruction () = contents of [] = Indirect addressing Condition codes : Condition CR contents for it to pass 0 =0 1 =1 2 =2 3 =3 4 <>0 5 <>1 6 <>2 7 Always In general, CR = 0 zero CR = 1 +ve CR = 2 -ve CR = 3 Overflow Instruction Set Name Mnemonic Opcode Operation Transfer word TW 1 0000 R1 Mode R2 0 R1 := M 1 0000 R1 Mode R2 1 M := R1 Add word AD 1 0010 R1 Mode R2 L/S R1 := R1 + M Subtract SU 1 0011 R1 Mode R2 L/S R1 := R1 - M And (Intersect) I 1 0100 R1 Mode R2 L/S R1 := R1 & M Or (Union) U 1 0101 R1 Mode R2 L/S R1 := R1 | M Xor X 1 0110 R1 Mode R2 L/S R1 := R1 xor M 1's complement C1 1 1111 R1 Mode R2 L/S R1 := Not(R2) Transfer Byte TC 1 1100 R1 Mode R2 L/S R1(low) := (M)(High/Low) (Character) Bit 15 of address specifies Byte If mode = RR, then Halves of register are swapped (EC instruction) Compare Word CW 1 1101 R1 Mode R2 L/S R1 - M sets CR only Increment Memory IM 1 0010 0000 Mode R2 L/S M := M + 1 2's Complement C2 1 0011 0000 Mode R2 L/S M := -M Call Function CF 1 1110 R1 Mode R2 1 Push CR and PC (=A0) onto stack (Stack pointer =R1). Then set PC = M Return RT 1 1110 0000 Mode 01 R2 1 Return from subroutine, popping CR and PC off stack. Stack pointer = R2 Absolute Branch AB 1 0001 Cnd Mode R2 0 If condition, PC = M Load Constant LK 0 0000 R3 Data R3(low) := Data Add Constant AK 0 0010 R3 Data R3 := R3 + Data Subtract Const SK 0 0011 R3 Data R3 := R3 - Data And Const IK 0 0100 R3 Data R3 := R3 & Data Or Const UK 0 0101 R3 Data R3 := R3 | Data Xor Const XK 0 0110 R3 Data R3 := R3 Xor Data Relative Forward RF 0 1010 Cond Disp If Cond, PC := PC + Disp Relative Back RB 0 1011 Cond Disp If Cond, PC := PC - Disp Disp = 8 bit displacement PC is incremented by 2 before disp is added as part of the fetch cycle Branch Constant BK 0 0001 Cond Data If Cond, PC := Data Left Shift Arith LA 0 0111 R3 000 00001 R3 := R3 left shifted Right Shift Arit RA 0 0111 R3 001 00001 R3 := R3 right shifted Left Shift Logic LL 0 0111 R3 010 00001 R3 := R3 left shifted Right Rotate RC 0 0111 R3 111 00001 R3 := R3 rotated right Control I/O CT 0 1000 R3 1 F Dev Start/Stop I/O on specified device. F = 1 bit flag (=1 to start, 0 to stop). Dev = 6 bit device address. R3 is sent on I/O bus Input IN 0 1001 R3 0 F Dev R3 := Data from Device F (1 bit) is sent to device Send Status SS 0 1001 R3 1 1 Dev Read status word from device Output OT 0 1000 R3 0 F Dev Send R3 (and F bit) to device Test Status TS 0 1001 R3 1 0 Dev Bit 15 (LSB) of R3 set if device ready In all I/O instructions, CR is set to 0 if OK, 1 if instruction not accepted, 3 if device address unknown Read interrupt RL 0 1001 R3 00 0000000 Read interrupt line status lines into R3 Write interrupt WM 0 1000 R3 00 0000000 Inhibit interrupt lines Mask given by 1's in R3 Enable Interrupt EN 0 0101 000 01000000 Enable Interrupts Halt HT 0 0100 000 01111111 Halt CPU Reset Internal RI 0 0100 000 11 Dev 1 Reset internal CPU Interrupt interrupt. Dev is a 5 bit field specifying the interrupting device. Bit 10 = Control panel Bit 11 = power fail Bit 12 = Clock Bit 13 = Error Inhibit Inters IH 0 0100 000 10111111 Disable Interrupts Lnk to Monitor LM 0 0101 000 00000100 Link to monitor - Call routing indirectly through address 40 hex